A10-DATASHEET
2015.12.31
16
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 12: Internal Weak Pull-Up Resistor Values for Arria 10 Devices—Preliminary
Symbol
Description
Condition (V) (20)
Value (21)
Unit
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
VCCIO = 3.0 5%
25
25
25
25
25
25
25
VCCIO = 2.5 5%
VCCIO = 1.8 5%
VCCIO = 1.5 5%
VCCIO = 1.35 5%
VCCIO = 1.25 5%
VCCIO = 1.2 5%
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
RPU
Table 13: Internal Weak Pull-Down Resistor Values for Arria 10 Devices—Preliminary
Pin Name
Description
Condition (V)
Value (21)
Unit
nIO_PULLUP
Dedicated input pin that determines the
internal pull-ups on user I/O pins and dual-
purpose I/O pins.
VCC = 0.9 3.33%
25
kΩ
VCCPGM = 1.8 5 %
VCCPGM = 1.5 5%
VCCPGM = 1.2 5%
VCCPGM = 1.8 5%
VCCPGM = 1.5 5%
VCCPGM = 1.2 5%
25
25
25
25
25
25
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
TCK
Dedicated JTAG test clock input pin.
Configuration input pins that set the
MSEL[0:2]
configuration scheme for the FPGA device.
Related Information
Arria 10 Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
(20)
(21)
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
Valid with 25% tolerances to cover changes over PVT.
.
Arria 10 Device Datasheet
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