Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.12.06
Feature
Low-power serial
transceivers
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Description
Continuous operating range:
— Intel Arria 10 GX—1 Gbps to 17.4 Gbps
— Intel Arria 10 GT—1 Gbps to 25.8 Gbps
Backplane support:
— Intel Arria 10 GX—up to 12.5
— Intel Arria 10 GT—up to 12.5
Extended range down to 125 Mbps with oversampling
ATX transmit PLLs with user-configurable fractional synthesis capability
Electronic Dispersion Compensation (EDC) support for XFP, SFP+, QSFP, and CFP optical
module
Adaptive linear and decision feedback equalization
Transmitter pre-emphasis and de-emphasis
Dynamic partial reconfiguration of individual transceiver channels
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Dual-core ARM Cortex-A9 MPCore processor—1.2 GHz CPU with
1.5 GHz overdrive capability
256 KB on-chip RAM and 64 KB on-chip ROM
System peripherals—general-purpose timers, watchdog timers, direct
memory access (DMA) controller, FPGA configuration manager, and
clock and reset managers
Security features—anti-tamper, secure boot, Advanced Encryption
Standard (AES) and authentication (SHA)
ARM CoreSight* JTAG debug access port, trace port, and on-chip
trace storage
Hard memory interface—Hard memory controller (2,400 Mbps DDR4,
and 2,133 Mbps DDR3), Quad serial peripheral interface (QSPI) flash
controller, NAND flash controller, direct memory access (DMA)
controller, Secure Digital/MultiMediaCard (SD/MMC) controller
Communication interface— 10/100/1000 Ethernet media access
control (MAC), USB On-The-GO (OTG) controllers, I
2
C controllers,
UART 16550, serial peripheral interface (SPI), and up to 62
HPS GPIO interfaces (48 direct-share I/Os)
High-performance ARM AMBA* AXI bus bridges that support
simultaneous read and write
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and
lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue
transactions to slaves in the HPS, and vice versa
Configuration bridge that allows HPS configuration manager to
configure the core logic via dedicated 32-bit configuration port
FPGA-to-HPS SDRAM controller bridge—provides configuration
interfaces for the multiport front end (MPFE) of the HPS SDRAM
controller
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HPS
(Intel Arria 10 SX
devices only)
Processor and system
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External interfaces
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Interconnects to core
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Configuration
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Tamper protection—comprehensive design protection to protect your valuable IP investments
Enhanced 256-bit advanced encryption standard (AES) design security with authentication
Configuration via protocol (CvP) using PCIe Gen1, Gen2, or Gen3
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Intel Arria 10 devices support this external memory interface using hard PHY with soft
memory controller.
Intel
®
Arria
®
10 Device Overview
6
INTEL [ INTEL CORPORATION ]
