Intel® Arria® 10 Device Overview
A10-OVERVIEW | 2018.12.06
Maximum Resources
Table 10.
Maximum Resource Counts for Intel Arria 10 GT Devices
Resource
Product Line
GT 900
900
GT 1150
1,150
Logic Elements (LE) (K)
ALM
339,620
1,358,480
48,460
9,386
1,518
3,036
32
427,200
1,708,800
54,260
12,984
1,518
Register
Memory (Kb)
M20K
MLAB
Variable-precision DSP Block
18 x 19 Multiplier
PLL
3,036
Fractional Synthesis
I/O
32
16
16
(5)
(5)
Transceiver
17.4 Gbps
25.8 Gbps
72
72
6
6
GPIO(6)
624
312
4
624
312
4
LVDS Pair(7)
PCIe Hard IP Block
Hard Memory Controller
16
16
Related Information
Intel Arria 10 GT Channel Usage
Configuring GT/GX channels in Intel Arria 10 GT devices.
Package Plan
Table 11.
Package Plan for Intel Arria 10 GT Devices
Refer to I/O and High Speed I/O in Intel Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and
LVDS channels in each device package.
SF45
(45 mm × 45 mm, 1932-pin FBGA)
Product Line
3 V I/O
LVDS I/O
624
XCVR
72
GT 900
—
—
GT 1150
624
72
(5)
If all 6 GT channels are in use, 12 of the GX channels are not usable.
(6)
(7)
The number of GPIOs does not include transceiver I/Os. In the Intel Quartus Prime software,
the number of user I/Os includes transceiver I/Os.
Each LVDS I/O pair can be used as differential input or output.
Intel® Arria® 10 Device Overview
Send Feedback
13
INTEL [ INTEL ]
