IN74HC299
FUNCTION TABLE
Inputs
Response
Mode Rese Mode
Output Clock Serial PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’
Select Enables Inputs QA QB QC QD QE QF QG QH
t
S2 S1 OE1 OE2
DA DH
Reset
L
L
X
L
L
X
H
H
L
L
X
H
L
L
X
X
X
X
X
X
D
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
X
QA through QH=Z
L
L
Shift
H
Shift Right: QA through QH=Z;
DA FA; FA FB; etc
Shift Right: QA through QH=Z;
DA FA; FA FB; etc
Shift Right: DA FA =QA;
FA FB =QB; etc
D
QG
Right
H
H
H
H
H
H
L
L
H
H
L
X
L
H
L
D
D
X
X
X
X
X
X
D
D
D
X
D
D
QG
QG
D
Shift
Left
H
H
H
H
H
X
L
X
H
L
Shift Left: QA through QH=Z; QB
DH FH; FH FG; etc
L
Shift Left: QA through QH=Z; QB
D
DH
FH; FH
FG; etc
L
Shift Left: DH
FH =QH;
QB
D
FH
FG =QG; etc
Parallel
Load
Hold
H
X
X
Parallel Load:PN
FN
PA PH
H
H
H
L
L
L
L
L
L
H
X
L
X
H
L
X
X
X
X
X
X
X Hold: QA through QH=Z; FN=FN PA PH
X Hold: QA through QH=Z; FN=FN PA PH
X
Hold: QN =QH
PA PH
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the
high-
impedance state; however, sequential operation or clearing of the register is not affected.
6
INTEGRAL [ INTEGRAL CORP. ]
