TECHNICAL DATA
IN74AC573
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74AC573 is identical in pinout to the LS/ALS573,
HC/HCT573. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
ORDERING INFORMATION
IN74AC573N Plastic
IN74AC573DW SOIC
TA = -40° to 85° C for all packages
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=VCC
PIN 10 = GND
Inputs
Latch
Output
Q
Output
D
Enable Enable
L
H
H
L
H
L
H
L
L
no change
Z
L
X
X
H
X
X = don’t care
Z = high impedance
456
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