TECHNICAL DATA
IN74AC112
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC112 is identical in pinout to the LS/ALS112,
HC/HCT112. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
ORDERING INFORMATION
IN74AC112N Plastic
IN74AC112D SOIC
TA = -40° to 85° C for all
packages
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
Outputs
Set
L
Reset
H
J
K
X
X
X
L
Q
Q
L
X
X
X
X
X
X
L
H
L
L*
H
L
L
H
L*
L
H
H
H
H
H
H
H
H
No Change
H
L
H
L
L
H
L
H
H
H
X
X
X
H
H
H
X
X
X
Toggle
H
L
No Change
No Change
No Change
H
H
H
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
PIN 16=VCC
PIN 8 = GND
X = Don’t Care
127
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