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IN74AC109N 参数 Datasheet PDF下载

IN74AC109N图片预览
型号: IN74AC109N
PDF下载: 下载PDF文件 查看货源
内容描述: 双JK触发器具有​​置位和复位高速硅栅CMOS [Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS]
分类和应用: 触发器
文件页数/大小: 5 页 / 173 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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IN74AC109  
AC ELECTRICAL CHARACTERISTICS  
(CL=50pF,Input tr=tf=3.0 ns)  
*
VCC  
V
Guaranteed Limits  
Symbol  
Parameter  
Unit  
25 °C  
-40°C to  
85°C  
Min  
Max  
Min  
Max  
fmax  
tPLH  
tPHL  
tPLH  
tPHL  
CIN  
Maximum Clock Frequency (Figure 1)  
3.3  
5.0  
125  
150  
100  
125  
MHz  
ns  
Propagation Delay , Clock to Q or Q  
(Figure 1)  
3.3  
5.0  
4.0  
2.5  
13.5  
10.0  
3.5  
2.0  
16.0  
10.5  
Propagation Delay , Clock to Q or Q  
(Figure 1)  
3.3  
5.0  
3.0  
2.0  
14.0  
10.0  
3.0  
1.5  
14.5  
10.5  
ns  
Propagation Delay , Set or Reset to Q or Q  
(Figure 2)  
3.3  
5.0  
3.0  
2.5  
12.0  
9.0  
2.5  
2.0  
13.0  
10.0  
ns  
Propagation Delay , Set or Reset to Q or Q  
(Figure 2)  
3.3  
5.0  
3.0  
2.0  
12.0  
9.5  
3.0  
2.0  
13.5  
10.5  
ns  
Maximum Input Capacitance  
5.0  
4.5  
4.5  
pF  
Typical @25°C,VCC=5.0 V  
CPD  
Power Dissipation Capacitance  
35  
pF  
*Voltage Range 3.3 V is 3.3 V ±0.3 V  
Voltage Range 5.0 V is 5.0 V ±0.5 V  
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=3.0 ns)  
*
VCC  
Guaranteed Limits  
Symbol  
Parameter  
V
Unit  
ns  
25 °C  
-40°C to  
85°C  
tsu  
th  
Minimum Setup Time, J or K to Clock (Figure  
3)  
3.3  
5.0  
6.5  
4.5  
7.5  
5.0  
Minimum Hold Time, Clock to J or K (Figure  
3)  
3.3  
5.0  
0
0.5  
0
0.5  
ns  
tw  
Minimum Pulse Width, Set, Reset, Clock  
(Figures 1,2)  
3.3  
5.0  
4.0  
3.5  
4.5  
3.5  
ns  
trec  
Minimum Recovery Time, Set or Reset to  
Clock (Figure 2)  
3.3  
5.0  
0
0
0
0
ns  
*Voltage Range 3.3 V is 3.3 V ±0.3 V  
Voltage Range 5.0 V is 5.0 V ±0.5 V  
120