TECHNICAL DATA
IN7472
AND-Gated J-K Master-Slave Flip-
Flops with Reset and Clear
LOGIC DIAGRAM
ORDERING INFORMATION
IN7472N Plastic
IN7472D SOIC
TA = -10° to 70° C for all packages
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
NC - No internal connection
FUNCTION TABLE
Inputs
Output
Reset Clear Clock
J
K
X
X
X
L
Q
Q
L
L
H
L
H
L
X
X
X
X
X
X
L
H
L
H*
Q0
H
H
L
H*
Q0
L
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
H
TOGGLE
X =don’t care
Q0 = the level of Q before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level on each
active transition (pulse) of the clock.
*This configuration is nonstable; that is, it will not persist whenpreset and clear inputs
return to their inactive (high) level.
1
INTEGRAL [ INTEGRAL CORP. ]
