IN24LC04B/08B
Figure 2. Bus timing Start/Stop
AC CHARACTERISTICS
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Parameter
Symbol
Units Remarks
Min
Max
100
-
Min
Max
400
-
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
FCLK
THIGH
TLOW
TR
-
4000
4700
-
-
600
1300
-
kHz
ns
ns
ns Note 2
ns Note 2
-
-
1000
300
300
300
TF
-
-
After this period the
first clock pulse is
generated
THD:STA
4000
-
600
-
ns
Only relevant for
repeated START
condition
START condition setup time
TSU:STA
4700
-
600
-
ns
Data input hold time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
250
4000
-
-
-
-
0
100
600
-
-
-
-
ns
ns
ns
Data input setup time
STOP condition setup time
Output valid from clock
3500
900
ns Note 1
Time the bus must be
free before a new
transmission can start
Bus free time
TBUF
TOF
TSP
4700
-
1300
-
ns
Output fall time from VIH min
to VIL max
Input filter spike suppres-sion
(SDA & SCL pins)
Note2,
ns
-
-
-
250
50
20+0.1CB
250
50
CB≤100pF
Note 3
-
-
ns
Write cycle time
Byte or Page
TWR
10
10
ms
mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined
region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or
STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide
improved noise and spike suppression. This eliminates the need for a Ti specification for standard
operation.
3
INTEGRAL [ INTEGRAL CORP. ]
