IN24LC04B/08B
Figure 8. Page Write
Figure 9. Current Address Read
Figure 10. Random Read
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the
IN24LC04B/08B transmits the first data byte, the master issues an acknowledge as opposed to a
stop condition in a random read. This directs the IN24LC04B/08B to transmit the next sequentially
addressed 8 bit word (see Figure 11).
To provide sequential reads the IN24LC04B/08B contains an internal address pointer which is
incremented by one at the completion of each operation. This address pointer allows the entire
memory contents to be serially read during one operation.
Noise Protection
The IN24LC04B/08B employs a Vcc threshold detector circuit which disables the internal
erase/write logic if the Vcc is below 1,5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to
assure proper device operation even on a noisy bus.
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