IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
I/O for Memory, SIU, DMA, Interrupts, and Timers
Port 0
Port 2
Port 1
Port 3
ADDR/DATA/IO
Addr/Data/IO
SPCL FUNC/IO
SPCL FUNC/IO
Memory
Control
Control
XTAL
Reset
Clock Gen.
& Timing
192x8 Dual Port
RAM
C8051
CPU
Address/Data
Timers
SIU
Interrupts
Figure 5. Functional Block Diagram
®
IA211010112-04
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