IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Pin
Signal
lcs_n
Name
lcs_n
PLCC
33
PQFP
46
LQFP
63
Description
lower chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock_n
lock_n
48
28
45
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress cannot be interrupted. While lock_n
is active, the IA186XL will not service bus
requests such as HOLD.
When resin_n is active, this pin is weakly held
high and must not be driven low.
mcs0_n mcs0_n/pereq
mcs1_n mcs1_n/error_n 37
38
39
40
41
42
57
58
59
60
mid-range memory chip select. Output.
mcs2_n
mcs2_n
36
35
mcs3_n mcs3_n/nps_n
n.c.
nmi
n.c.
nmi
NA
2, 11,
14, 15,
24, 43,
44, 62,
63
4, 25,
35, 55,
72
not connected.
46
30
47
non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high) it
causes a Type 2 interrupt.
nps_n
mcs3_n/nps_n
pcs0_n
35
25
27
28
29
30
31
32
38
42
54
52
51
50
49
48
47
39
60
71
69
68
67
66
65
64
57
numeric processor select
peripheral chip select signals 0–6. Output.
pcs0_n
pcs1_n
pcs2_n
pcs3_n
pcs4_n
pcs5_n
pcs6_n
pereq
pcs1_n
pcs2_n
pcs3_n
pcs4_n
pcs5_n/a1
pcs6_n/a2
mcs0_n/pereq
numerics coprocessor external request.
Input. Active High. When asserted (high), this
signal indicates that a data transfer between
an Intel 80C187 Numerics Coprocessor and
the CPU is pending.
®
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