IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
4.5
Ports
Ports P0, P1, P2, and P3 are SFRs. The contents of the SFR can be observed on corresponding
pins on the chip. Writing a ―1‖ to any of the ports causes the corresponding pin to be at high level
(VCC), and writing a ―0‖ causes the corresponding pin to be held at low level (GND).
All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P3), an
output driver, and an input buffer, so the CPU can output or read data through any of these ports if
they are not used for alternate purposes.
Ports P0, P1, P2, and P3 can perform some alternate functions. Ports P0 and P2 are used to access
external memory. In this case, port ―p0‖ outputs the multiplexed lower eight bits of address with
―ALE‖ strobe high and then reads/writes eight bits of data. Port P2 outputs the higher eight bits of
address. Keeping ―ea‖ pin low (tied to GND) activates this alternate function for Ports P0 and P2.
Port P3 and P1 can perform some alternate functions. The pins of Port P3 are multifunctional.
They can perform the additional functions described in Table 10.
Table 10. Additional Functions of Port P3
Pin
Symbol
Function
P3.0 RxD, I/O
In point-to-point or multipoint configurations (SMD.3 = 0) this pin is I/O and signals
the direction of data flow on DATA (P3.1). In loop mode (SMD.3 = 1) and
diagnostic mode this pin is RxD, Receive Data input.
P3.1 TxD, DATA In point-to-point or multipoint configurations (SMD.3 = 0) this pin is DATA and is
the transmit/receive data pin. In loop mode (SMD.3 = 1) this pin is the transmit
data, TxD pin. Writing a ―0‖ to this port buffer bit enables the diagnostic mode.
P3.2 INT0
P3.3 INT1
P3.4 T0
External Interrupt 0 input. Also gate control input for Counter 0.
External Interrupt 1 input. Also gate control input for Counter 1.
Timer/Counter 0 external input. Setting the appropriate bits in the Special
Function Registers TCON and TMOD activates this function.
Timer/Counter 1 external input. Setting the appropriate bits in the SFRs TCON
and TMOD activates this function. Can also function as the external clock source
for the SIU.
P3.5 T1, SCLK
P3.6 WR
P3.7 RD
External Data Memory write strobe, active LOW. This function is activated by a
CPU write access to External Data Memory (i.e., MOVX @DPTR, A).
External Data Memory read strobe, active LOW. This function is activated by a
CPU read access from External Data Memory (i.e., MOVX A, @DPTR).
Request To Send output, active low.
P1.6 RTS
P1.7 CTS
Clear To Send input, active low.
4.6
Port Registers
4.6.1 Port 0 (P0)
Table 11 presents the values for Port 0 (P0), a general purpose, 8-bit, I/O port and multiplexed low
order address and data bus with open-drain output buffers.
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