IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
Name
PLCC
28
27
26
25
24
21
20
19
LQFP
16
15
14
13
12
9
PQFP
59
58
57
56
55
52
51
50
Description
gcs0_n p1.0/gcs0_n
gcs1_n p1.1/gcs1_n
gcs2_n p1.2/gcs2_n
gcs3_n p1.3/gcs3_n
gcs4_n p1.4/gcs4_n
gcs5_n p1.5/gcs5_n
gcs6_n p1.6/gcs6_n
gcs7_n p1.7/gcs7_n
generic chip select n (n = 0–7). Output. Active
Low. When programmed and enabled, each of
these pins provide a chip select signal that will
be asserted (low) whenever the address of a
memory or I/O bus cycle is within the address
space programmed for that output.
8
7
hlda
hlda
12
1
44
hold acknowledge. Output. Active High.
When hlda is asserted (high), it indicates that
the IA188EB has relinquished control of the
local bus to another bus master in response to
a HOLD request (see next table entry).
When hlda is asserted, the IA188EB data bus
and control signals are floated, allowing another
bus master to drive the signals directly.
hold
(input)
hold
(input)
13
2
45
hold. Input. Active High. This signal is a
request indicating that an external bus master
wishes to gain control of the local bus. The
IA188EB will relinquish control of the local bus
between instruction boundaries not conditioned
by a lock prefix.
int0
(input)
int1
(input)
int0
(input only)
int1
(input only)
31
32
19
20
62
63
interrupt N (N = 0–4). Input/Output. Active
High. These maskable inputs interrupt program
flow and cause execution to continue at an
interrupt vector of a specific interrupt type as
follows:
int2
int2/inta0_n
int3/inta1_n
33
34
35
21
22
23
64
65
66
int0: Type 12
int1: Type 13
int2: Type 14
int3: Type 15
int4: Type 17
int3
int4 (input)
int4
(input only)
To allow interrupt expansion, int0 and int1 can
be used with the interrupt acknowledge signals
inta0_n and inta1_n (see next table entries) to
serve as external interrupt inputs or interrupt
acknowledge outputs.
inta0_n
int2/inta0_n
33
21
64
interrupt acknowledge 0. Output. Active Low.
This pin provides an interrupt acknowledge
handshake in response to an interrupt request
on the int0 pin (see previous table entry).
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