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IA88C00 参数 Datasheet PDF下载

IA88C00图片预览
型号: IA88C00
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontroller]
分类和应用: 微控制器
文件页数/大小: 80 页 / 674 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA88C00  
Data Sheet  
Microcontroller  
As of Production Version -01  
Once the complete character is assembled, the UART checks it and performs the following actions:  
1. Sets the Control Character status bit, if it is an ASCII control character.  
2. Checks the wake-up settings and completes any indicated action.  
3. Checks to see if the calculated parity matches the programmed parity bit, if parity is enabled. If they  
do not match, it sets the parity Error bit in URC (R236, Bank 0), which remains set until reset by  
software.  
4. Resets the Framing Error bit (URC, bit 4), if the character is assembled without any stop bits. This bit  
remains set until cleared by software.  
Overrun errors occur when characters are received faster than they are read. That is, when the UART has  
assembled a complete character before the CPU has read current character, the UART sets the Overrun  
Error bit (URC, bit 3), and the character currently in the receive buffer is lost.  
The overrun bit remains set until cleared by software.  
Address Space  
The IA88C00 can access 64 Kbytes of program memory and 64 Kbytes of data memory. These spaces can  
be either combined or separate. If separate, they are controlled by the DM line (Port P35), which selects  
data memory when Low and program memory when High.  
CPU Program Memory  
Program memory occupies address 0 to 64K. External program memory is accessed by configuring Ports  
0 and/or 1 and/or 4 as the memory interface.  
The address/data lines are controlled by AS, DS and R/W.  
The first 32 program memory bytes are reserved for interrupt vectors. The lowest address available for  
user programs is 32 (decimal). This value is automatically loaded into the program counter after a  
hardware reset. Port 0 can be configured to provide from 0 to 8 additional address lines. Port 1 is used as  
an 8-bit multiplexed address/data port or as a data port when in de-mux mode.  
CPU Data Memory  
If separated from program memory by the DM optional output, the external CPU data memory space can  
be mapped anywhere from 0 to 64K (full 16-bit address space). Data memory uses the same address/data  
bit (Port 1) and additional address (chosen from Port 0) as program memory. The DM pin (P35) is mainly  
what distinguishes data memory from program memory. It is also distinguished by the fact that data  
memory can begin at address 0000H.  
Figure 62 shows the system memory space.  
Copyright 2005  
Innovasic.com  
Innovasic Semiconductor  
ENG21 1 030617-04  
www.Innovasic  
1.888.824.4184  
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