IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Architecture
IA88C00 maintains program model compatibility with the Super8 architecture, including 268 general
purpose registers and 57 registers for control and mode functions.
The instruction set, is also fully binary compatible supporting all instructions, including multiply and
divide instructions and provisions for BCD operations.
The peripheral set maintains register/ program model compatibility. Robust serial communications are
provided by an on-board UART. Counter/timers are provided for time-sensitive/control loop
applications. A watchdog timer is provided for processor sanity.
Pin Descriptions
The rising edge of this output indicates that address, R/W, and DM (when
/AS Address Strobe
(output, active Low) appropriate) are valid.
The leading edge of this signal indicates that data is valid during a write cycle.
/DS Data Strobe
(output, active Low
The trailing edge of this signal is used to latch data into the IA88C00 during a
read cycle.
Input/Output Ports configured under program control. Specific functions include:
P00-P07, P10-P17,
P20-P27, P30-P37,
P40-P47, Port I/O
Lines (input/output)
Port 1 serves as the multiplexed address/data port. It serves as the data bus
de-multiplexed mode, and Port 0 pins can be used as additional address
lines or general purpose I/O.
Ports 2 and 3 provide support for interrupts, the UART and the timers.
Alternatively, they can be programmed as general purpose I/O.
Port 4 is used for general I/O or as the lower address byte in de-mux mode.
/RESET (input,
active Low)
Reset input. Reset vector is address 0020H.
When high, the current bus operation is a read. When low, the current bus
operation is a write.
R/W Read/Write
(output)
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