IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Functional Block Diagram
I/O for Memory, SIU, DMA, Interrupts, Timers
Port 0
Port 2
Port 1
Port 3
ADDR/DATA/IO
ADDR/DATA/IO
SPCL FUNC/IO
SPCL FUNC/IO
Memory
Control
Control
Clock Gen.
& Timing
192x8Dual Port
RAM
C8051
CPU
XTAL
Reset
Address/Data
Interrupts
SIU
Timers
Copyright 2003
ENG210010112-00
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