IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 17. Mode 3: Synchronous Operation Timing for 3.3V Operation
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tEHDV
Parameter
Minimum
8 MHz
4 MHz
2 MHz
–
Maximum
16 MHz
10 MHz
8 MHz
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
e High to Data Valid (for High-Speed Registers 02H,
04H, and 5H)
60 ns
e High to Data Valid (for Low-Speed Registers) Read
Cycle without Previous Write
e High to Data Valid (for Low-Speed Registers) Read
Cycle with Previous Write
–
–
1.5 tMCLK + 100
ns
a
3.5 tMCLK + 100
ns
tELDH
tELDZ
tELDV
tAVEH
tELAV
tCVEH
tELCV
tDVEL
tEHEL
tAVAV
tAVCL
tCHAI
tCOPD
Data Hold after e Low for a Read Cycle
Data Float after e Low
Data Hold after e Low for a Write Cycle
Address and r-w_n to e Setup
Address and r-w_n Valid after e Falls
cs_n Valid to e High
cs_n Valid after e Low
Data Setup to e Low
e Active Width
Start of a Write Cycle after a Previous Write Access
Address or r-w_n to cs_n Low Setup
cs_n High Address Invalid
clkout Period (CDV is the value loaded in the CLKOUT
Register representing the clkout divisor)
5 ns
–
15 ns
25 ns
15 ns
0 ns
–
50 ns
–
–
–
–
–
–
–
–
–
–
0 ns
55 ns
100 ns
2 tMCLK
3 ns
7 ns
(CDV + 1) × tOSC
tCHCL
clkout High Period (CDV is the value loaded in the
CLKOUT Register representing the clkout divisor)
(CDV + 1) × ½
(CDV + 1) × ½
tOSC – 10
tOSC + 15
a
A “Read Cycle without Previous Write” is where a read cycle follows a write cycle and where the falling
edge of e for the write cycle and the rising edge of e for the read cycle are separated by at least 2 × tMCLK
.
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