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IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
Figure 8: External Data Memory Write Cycle
ALE
PSENn
TLLWL
TLLAX
TWLWH
TWHLH
WRn
TAVLL
TQVWX
TWHQX
A0-A7 FROM R OR DPL
A0-A7 FROM PCL
PORT0
PORT2
DATA OUT
INSTR. IN
TAVWL
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Table 10: External Clock Drive
Symbol
1/TCLCL
TCHCX
TCLCX
TCLCH
TCHCL
Parameter
Oscillator Frequency
High Time
Min
3.5
20
Max
16.5
Units
MHz
ns
ns
ns
20
Low Time
Rise Time
Fall Time
20
20
ns
Figure 9: External Clock Drive Waveform
Vcc - 0.5
0.7 Vcc
0.2 Vcc - 0.1
0.45V
TCHCX
TCLCH
TCHCL
TCLCX
TCLCL
Copyright ã 2000
innovASIC
[_________The End of Obsolescenceä
INNOVASIC [ INNOVASIC, INC ]
