Page 19 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
CSMA/CD mode. In SDLC mode this bit indicates that 7 consecutive 1s were detected before an end flag but after
data was loaded into the receive FIFO. AE may also be set.
OR - This bit is set by the GSC to indicate that the receive FIFO was full and then new data was shifted into it. AE
and /or CRCE may also be set. This flag is cleared by the user.
SARL0, SARH0 (0A2h, 0A3h) - Source address register high and low bytes for DMA channel 0. The two registers
provide a 16-bit value representing the address of the source for a DMA transfer via channel 0. Valid address range is
from 0 to 65535.
SARL1, SARH1 (0B2h, 0B3h) - Source address register high and low bytes for DMA channel 1. The two registers
provide a 16-bit value representing the address of the source for a DMA transfer via channel 1. Valid address range is
from 0 to 65535.
SBUF (099h) - Writes to this register load the transmit register, and reads access the receive register.
SCON* (098h) - This register controls the set up of the UART as defined by the table below.
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
SM0, SM - The combination of these 2 bits controls the mode and type of baud rate.
Mode
SM0
SM1
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
(Osc. Freq.)/12
0
1
2
3
0
0
1
1
0
1
0
1
Variable
(Osc. Freq.)/64 or (Osc. Freq.)/32
Variable
SM2 - When this bit is set and the UART mode is 1, RI will not be activated unless a valid stop bit is received. When
this bit is set and the UART mode is 2 or 3, RI will not be activated if the 9th bit is 0.
REN - Setting this bit enables the UART to receive. Clearing this bit disables UART reception.
TB8 - In modes 2 and 3, the value of this bit is transmitted during the 9th bit time. This bit is set or cleared by
software.
RB8 - In modes 2 and 3, this bit is the value of the 9th bit that was received by the UART. In mode 1, this bit is the
value of the stop bit received by the UART.
TI - Transmit Interrupt flag set by hardware upon at the end of the 8th bit in mode 0 or at the beginning of the stop
bit in modes 1, 2, or 3. This bit must be cleared by software to clear the interrupt.
RI - Receive Interrupt flag set by hardware at the end of the 8th bit in mode 0 or halfway through the stop bit in
modes 1, 2, or 3. This bit must be cleared by software to clear the interrupt.
SLOTTM (0B4h) - Determines the length of the slot time in CSMA/CD mode. A slot time equals SLOTTM * (1 /
baud rate). Reads from this location are unreliable since this register is clocked asynchronously to the CPU. Loading a
value of 0 results in a slot time of 256 bit times.
SP (081h) - This register is the stack pointer. Its value points to the memory location that is the beginning of the stack.
TCDCNT (0D4h) - If probabilistic CSMA/CD is used this register contains the number of collisions. The user must
clear this register before transmitting a new frame so the GSC can distinguish between a new frame and the retransmit of a
frame. In deterministic backoff mode TCDCNT is used to hold the maximum number of slots.
TCON* (088h) - This register controls the operation of the Timers 0 and 1 and External Interrupts 0 and 1 as defined by
the table below.
Copyright ã 2000
innovASIC
[_________The End of Obsolescenceä
INNOVASIC [ INNOVASIC, INC ]
