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IA80C152JB 参数 Datasheet PDF下载

IA80C152JB图片预览
型号: IA80C152JB
PDF下载: 下载PDF文件 查看货源
内容描述: 通用通信控制器 [UNIVERSAL COMMUNICATIONS CONTROLLER]
分类和应用: 通信控制器
文件页数/大小: 32 页 / 234 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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Page 17 of 32  
IA80C152  
Preliminary Data Sheet  
UNIVERSAL COMMUNICATIONS CONTROLLER  
to a 1 selects the alternate collision resolution algorithm. Also disabled by setting this bit is the retriggering of the IFS  
on the reappearance of the carrier. Alternate Backoff mode must be used with this feature. The user must initialize  
TCDCNT with the maximum number of slots that are appropriate for the system. To disable the PBRS this register  
must be set to all 1s.  
DCJ - A 1 selects DC type jam. A 0 selects AC type jam.  
P0*, P1*, P2*, P3*, P4*, P5, P6 (080h, 090h, 0A0h, 0C0h, 091h, 0A1h) - These registers are for I/O as defined in the  
table below. Most registers have a dual function. P5 and P6 are not bit addressable and are only available in the JB and JD  
versions of the IC.  
Port  
Function  
Bit Address  
Function  
Bit Address  
Function  
Bit Address  
Function  
Bit Address  
Function  
Bit Address  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
P0  
P1  
P2  
P3  
P4  
P5  
P6  
Multiplexed Address/Data  
087h  
-
097h  
086h  
HLDA  
096h  
085h  
HLD  
095h  
084h  
RXCn  
094h  
083h  
TXCn  
093h  
082h  
DENn  
092h  
081h  
GTXD  
091h  
080h  
GRXD  
090h  
Address and User Defined  
0A7h  
RDn  
0B7h  
0A6h  
WRn  
0B6h  
0A5h  
T1  
0B5h  
0A4h  
T0  
0B4h  
User Defined  
0C4h  
User Defined  
091h  
User Defined  
0A1h  
0A3h  
INT1n  
0B3h  
0A2h  
INT0n  
0B2h  
0A1h  
TXD  
0B1h  
0A0h  
RXD  
0B0h  
0C7h  
0C6h  
0C5h  
0C3h  
0C2h  
0C1h  
0C0h  
Function  
Bit Address  
Function  
Address  
PCON (087h) - The POwer CONtrol register controls the power down and idle states of the 80C152 as well as various  
UART, GSC, and DMA functions as defined below.  
7
6
5
4
3
2
1
0
SMOD  
ARB  
REQ  
GAREN  
XRCLK  
GFIEN  
PD  
IDL  
SMOD - Doubles the baud rate of the UART if the bit is set to 1.  
ARB - The DMA (both channels) is put into ARBiter mode if the bit is set to 1.  
REQ - The DMA (both channels) is put into REQuester mode if the bit is set to 1.  
GAREN - The GSC Auxiliary Receive Enable allows the GSC to receive back-to-back SDLC frames by setting the bit  
to 1. This bit has no effect in CSMA mode.  
XRCLK - Setting this bit enables the External Receive Clock to be used by the receiver portion of the GSC.  
GFIEN - The GSC Flag Idle Enable bit generates idle flags between transmitted SDLC frames when this bit is set to a  
1. This bit has no effect in CSMA mode.  
PD - The Power Down bit puts the 80C152 into the power down power saving mode by setting this bit to a 1.  
IDL - The IDLe bit puts the 80C152 into the idle power saving mode by setting this bit to a 1.  
PRBS (0E4h) - This register contains the pseudo-random number to be used in the CSMA/CD backoff algorithm. The  
number is generated by using a feedback shift register clocked by the CPU phase clocks. Writing all 1s to this register will  
cause the register to freeze at all 1s. Writing any other value to it will cause it to start again. A read of this register will not  
always give the seed value due to the register being clocked by the CPUs phase clocks.  
Copyright ã 2000  
innovASIC  
[_________The End of Obsolescenceä