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IA8044_10 参数 Datasheet PDF下载

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型号: IA8044_10
PDF下载: 下载PDF文件 查看货源
内容描述: SDLC通信控制器 [SDLC Communications Controller]
分类和应用: 通信控制器
文件页数/大小: 65 页 / 597 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA8044/IA8344  
Data Sheet  
SDLC Communications Controller  
March 30, 2010  
LIST OF TABLES  
Table 1. IA8044 and IA8344 40-Lead PDIP Pin Listing..............................................................12  
Table 2. IA8044 and IA8344 44-Pin PLCC Pin Listing...............................................................15  
Table 3. IA8044 and IA8344 Absolute Maximum Ratings..........................................................17  
Table 4. IA8044 and IA8344 DC Characteristics.........................................................................17  
Table 5. Input/Output Characteristics of IC Signals.....................................................................19  
Table 6. Reset Vectors ..................................................................................................................20  
Table 7. SFR Bit Addressable Locations......................................................................................22  
Table 8. Internal RAM Bit Addressable Locations ......................................................................22  
Table 9. Special Function Registers..............................................................................................23  
Table 10. Additional Functions of Port P3 ...................................................................................24  
Table 11. Port 0 Register ..............................................................................................................25  
Table 12. Port 1 Register ..............................................................................................................25  
Table 13. Port 2 Register ..............................................................................................................25  
Table 14. Port 3 Register ..............................................................................................................26  
Table 15. Timer Mode Register....................................................................................................27  
Table 16. Timer Mode Select Bits ................................................................................................28  
Table 17. Timer Control Register .................................................................................................28  
Table 18. Timer 0 High Byte Register..........................................................................................29  
Table 19. Timer 0 Low Byte Register ..........................................................................................29  
Table 20. Timer 1 High Byte Register..........................................................................................29  
Table 21. Timer 1 Low Byte Register ..........................................................................................29  
Table 22. Accumulator Register ...................................................................................................32  
Table 23. B Register .....................................................................................................................32  
Table 24. Program Status Word Register .....................................................................................32  
Table 25. RS1/RS0 Bank Selections by State...............................................................................33  
Table 26. Stack Pointer.................................................................................................................33  
Table 27. Data Pointer (High) Register ........................................................................................33  
Table 28. Data Pointer (Low) Register.........................................................................................33  
Table 29. Interrupt Priority Register.............................................................................................35  
Table 30. Interrupt Enable Register..............................................................................................36  
Table 31. Serial Mode Register ....................................................................................................37  
Table 32. Serial Mode Select Clock Mode Bits............................................................................38  
Table 33. Status/Command Register.............................................................................................38  
Table 34. Send/Receive Count Register .......................................................................................39  
Table 35. Station Address Register...............................................................................................40  
Table 36. Transmit Buffer Start Address Register........................................................................40  
Table 37. Transmit Buffer Length Register..................................................................................40  
Table 38. Transmit Control Byte Register....................................................................................41  
Table 39. Receive Buffer Start Address Register .........................................................................41  
Table 40. Receive Buffer Length Register ...................................................................................41  
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