IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
Table 54. Logic Operations
Mnemonic
Description
Byte Cycle
ANL A,Rn
AND register to accumulator
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
ANL A,direct
ANL A,@Ri
ANL A,#data
ANL direct,A
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
ANL direct,#data AND immediate data to direct byte
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data OR immediate data to direct byte
XRL A,Rn
XRL A,direct
XRL A,@Ri
XRL A,#data
XRL direct,A
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
Exclusive OR indirect RAM to accumulator
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
XRL direct,#data Exclusive OR immediate data to direct byte
CLR A
CPL A
RL A
RLC A
RR A
Clear accumulator
Complement accumulator
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
RRC A
SWAP A
Rotate accumulator right through carry
Swap nibbles within the accumulator
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