Page 5 of 19
IA2910A
Preliminary Data Sheet
Microprogram Controller
I/O Signal Description
Table 1 below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
Table 1
Symbol
CLK
Type Description
I
I
I
I
I
I
Clock Input - Clock source for address register, microprogram
counter register, and stack file.
I(3:0)
CCn
Active high instruction bits. Selects instruction to be executed by the
IA2910A.
Active low. Condition code. Used as test criterion, pass is low on
CCn.
CCENn
RLDn
OEn
Active low. Condition code enable. When set high, CCn is ignored
and the IA2910A operates as it CCn were a low.
Active low. Clock enable to address register, allows loading of
register/counter regardless of instruction or condition.
Active low. Output enable, when high tri-states the output bus
YOUT.
CIN
FULLn
I
Active high. Carry in signal to the incrementer.
Active low. Indicates there are nine items on the stack.
Active high. Data bus input to the multiplexer.
Active high. Data bus output from the IA2910A.
O
I
DIN(11:0)
YOUT(11:0)
PLn
O
O
Active low. Pipeline address enable. Selects source number one
(usually pipeline register) as direct input source.
MAPn
O
O
Active low. Map address enable. Selects source number two (usually
mapping PROM or PLA) as direct input source.
VECTn
Active low. Vector address enable. Selects source number three
(usually interrupt starting address) as direct input source.
Theory of Operation
Table 2 shows the result of each instruction in controlling the mux which determines the YOUT
outputs, and in controlling the three enable signals PLn, MAPn, and VECTn. The effect on the
register/counter and the stack after the next positive-going clock edge is also shown. The mux
determines which internal source drives the YOUT outputs. The value loaded into the counter is
Copyright ã 1999, InnovASIC Inc.
Customer Specific IC Solutions
INNOVASIC [ INNOVASIC, INC ]
