Page 11 of 19
IA2910A
Preliminary Data Sheet
Microprogram Controller
transfer to the next instruction at address 53. If the test is failed, the next microinstruction at
address 94 will be executed. The program will continue to address 97 where the subroutine is
complete. To perform an unconditional RETURN-FROM-SUBROUTINE, the CRTN instruction
is executed unconditionally; the microinstruction at address 97 is programmed to force CCENn
HIGH, disabling the test and the forced PASS causes an unconditional return.
Instruction 11 CJPP is the CONDITIONAL JUMP PIPELINE register address and POP stack
instruction. This instruction provides another technique for loop termination and stack
maintenance. The example in Figure II shows a loop being performed from address 55 back to
address 51. The instructions at locations 52, 53, and 54 are all conditional JUMP and POP
instructions. At address 52, if the CCn input is LOW, a branch will be made to address 70 and the
stack will be properly maintained via a POP. Should the test fail, the instruction at location 53 (the
next sequential instruction) will be executed. Likewise, at address 53, either the instruction at 90 or
54 will be subsequently executed, respective to the test being passed or failed. The instruction at 54
follows the same rules, going to either 80 or 55. An instruction sequence as described here, using
the CJPP instruction, is very useful when several inputs are being tested and the microprogram is
looping waiting for any of the inputs being tested to occur before proceeding to another sequence
of instructions. This provides the powerful jump-table programming technique at the firmware
level.
Instruction 12 LDCT is the LOAD COUNTER AND CONTINUE instruction, which simply
enables the counter to be loaded with the value at its parallel inputs. These inputs are normally
connected to the pipeline branch address field which (in the architecture being described here)
serves to supply either a branch address or a counter value depending upon the microinstruction
being executed. There are altogether three ways of loading the counter – the explicit load by this
instruction 12; the conditional load included as part of instruction 4; and the use of the RLDn input
along with any instruction. The use of RLDn with any instruction overrides any counting or
decrementation specified in the instruction, calling for a load instead. Its use provides additional
microinstruction power, at the expense of one bit of microinstruction width. This instruction 12 is
exactly equivalent to the combination of instruction 14 and RLDn LOW. Its purpose is to provide
a simple capability to load the register/counter in those implementations which do not provide
microprogrammed control for RLDn.
Instruction 13 LOOP is the TEST END-OF-LOOP instruction, which provides the capability of
conditionally exiting a loop at the bottom; that is, this is a conditional instruction that will cause the
microprogram to loop, via the file, if the test is failed else to continue to the next sequential
instruction. The example in Figure II shows the LOOP microinstruction at address 56. If the test
fails, the microprogram will branch to address 52. Address 52 is on the stack because a PUSH
instruction had been executed at address 51. If the test is passed at instruction 56, the loop is
terminated and the next sequential microinstruction at address 57 is executed, which also causes the
stack to be POP’d; thus, accomplishing the required stack maintenance.
Instruction 14 CONT is the CONTINUE instruction, which simply causes the microprogram
counter to increment so that the next sequential microinstruction is executed. This is the simplest
microinstruction of all and should be the default instruction which the firmware requests whenever
there is nothing better to do.
Copyright ã 1999, InnovASIC Inc.
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