fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
TABLE OF CONTENTS
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2
Overview ............................................................................................................................... 7
1.1 Introduction to Device Level Ring Protocol................................................................ 8
1.2 Introduction to IEEE-1588........................................................................................... 9
Features ............................................................................................................................... 10
2.1 IEEE 802.3 MAC Details .......................................................................................... 11
2.1.1 IEEE 802.3 Full Duplex Flow Control ..................................................... 12
2.1.2 Half Duplex Flow Control and Broadcast/Multicast Storm Prevention ... 13
2.2 IEEE 1588 V2............................................................................................................ 13
2.2.1 IEEE 1588 Hardware Assist for Ordinary Clock...................................... 13
2.2.2 IEEE 1588 End to End Transparent Clock ............................................... 16
2.3 Device Level Ring (DLR) Protocol Support ............................................................. 17
2.3.1 Network Loops.......................................................................................... 18
2.4 Cut Through Forwarding ........................................................................................... 18
2.5 Quality of Service ...................................................................................................... 19
2.6 Unicast and Multicast Address Filtering ................................................................... 19
2.7 Statistics Counters...................................................................................................... 20
2.8 Buffer Management ................................................................................................... 20
2.9 Supported Network Topologies................................................................................. 21
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4
5
LQFP Package..................................................................................................................... 25
3.1 LQFP Package Pinout................................................................................................ 25
3.2 LQFP Pin Listing....................................................................................................... 26
3.3 LQFP Package Physical Dimensions......................................................................... 30
BGA Package ...................................................................................................................... 31
4.1 BGA Package Pinout ................................................................................................. 31
4.2 BGA Pin Listing ........................................................................................................ 32
4.3 BGA Package Physical Dimensions.......................................................................... 36
Electrical Characteristics..................................................................................................... 37
5.1 Thermal Characteristics ............................................................................................. 38
5.2 PLL Supply................................................................................................................ 38
5.3 System Clock Input.................................................................................................... 38
5.4 RESET: Power-On-Reset, Hardware Reset and Software Reset............................... 39
5.4.1 Power-On-Reset........................................................................................ 39
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