IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
6.
Reset Operation
The IA186EB/IA188EB will perform a reset operation any time the resin_n pin is active.
Figure 18 shows the reset sequence when power is applied to the IA186EB/IA188EB. An
external clock connected to clkin must not exceed the VCC threshold being applied to the
processor. This is normally not a problem if the clock driver is supplied with the same VCC that
supplies the processor. When attaching a crystal to the device, resin_n must remain active until
both VCC and clkout are stable (the length of time is application-specific and depends on the
startup characteristics of the crystal circuit). The resin_n pin is designed to operate correctly
using an RC reset circuit, but the designer must ensure that the ramp time for VCC is not so long
that resin_n is never really sampled at a logic low level when VCC reaches minimum operating
conditions.
Note: Failure to assert resin_n while the device is powering up will result in unpredictable
operation.
Figure 19, Warm Reset Timing, shows the timing sequence when resin_n is applied after Vcc is
stable and the device has been operating. Any bus operation that is in progress at the time
resin_n is asserted will terminate immediately.
While resin_n is active, bus signals lock_n, a19/once_n, and a18–a16 are configured as inputs
and weakly held high by internal pull-up transistors. Only a19/ once_n can be overdriven to a
low-to-enable ONCE Mode.
7.
Bus Timing
Figures 18 through 26 on the following pages present the various bus cycles that are generated
by the processor. The figures show the relationship of the various bus signals to clkout.
Together with the information present in AC Characteristics, the figures allow the user to
determine all the critical timing analysis needed for a given application.
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