欢迎访问ic37.com |
会员登录 免费注册
发布采购

EG80C188EB25 参数 Datasheet PDF下载

EG80C188EB25图片预览
型号: EG80C188EB25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 85 页 / 1257 K
品牌: INNOVASIC [ INNOVASIC, INC ]
 浏览型号EG80C188EB25的Datasheet PDF文件第44页浏览型号EG80C188EB25的Datasheet PDF文件第45页浏览型号EG80C188EB25的Datasheet PDF文件第46页浏览型号EG80C188EB25的Datasheet PDF文件第47页浏览型号EG80C188EB25的Datasheet PDF文件第49页浏览型号EG80C188EB25的Datasheet PDF文件第50页浏览型号EG80C188EB25的Datasheet PDF文件第51页浏览型号EG80C188EB25的Datasheet PDF文件第52页  
IA186EB/IA188EB  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
July 10, 2011  
4.1.7 I/O Port Unit  
The I/O Port Unit (IPU) on the IA186EB/IA188EB supports two 8-bit channels of input, output,  
or input/output operation. Port 1 is multiplexed with the chip select pins and is output only.  
Most of Port 2 is multiplexed with the serial channel pins.  
4.1.8 Refresh Control Unit  
The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to  
keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks  
between refresh requests.  
A 12-bit address generator is maintained by the RCU and is presented on the a1a12 address  
lines during the refresh bus cycle. Address Bits [a13a19] are programmable to allow the refresh  
address block to be located on any 8-Kbyte boundary.  
4.1.9 Power Management Unit  
The IA186EB/IA188EB Power Management Unit (PMU) is provided to control the power  
consumption of the device. The PMU provides three power modes: Active, Idle, and  
Powerdown.  
Active Mode indicates that all units on the IA186EB/IA188EB are functional and the device  
consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes  
the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate  
normally).  
The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal  
oscillator. All internal registers hold their values provided VCC is maintained. Current  
consumption is reduced to just transistor junction leakage.  
4.2  
Peripheral Architecture  
The IA186EB/IA188EB has integrated several common system peripherals with a CPU core to  
create a compact, yet powerful system. The integrated peripherals are designed to be flexible  
and provide logical interconnections between supporting units (e.g., the interrupt control unit  
supports interrupt requests from the timer/counters or serial channels). The list of integrated  
peripherals includes:  
7-Input Interrupt Control Unit  
3-Channel Timer/Counter Unit  
2-Channel Serial Communications Unit  
10-Output Chip-Select Unit  
I/O Port Unit  
Refresh Control Unit  
IA211080314-13  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.Innovasic.com  
Customer Support:  
Page 48 of 85  
1-888-824-4184