IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Pin
Signal
ale
Name
ale/qs0
PLCC
61
PQFP
10
LQFP
29
Description
address latch enable. Output. Active High.
This signal is used to latch valid address
information on the falling edge of ale during
the address portion of a bus cycle.
ardy
ardy
55
64
20
7
37
26
asynchronous ready. Input. Indicates to the
processor the addressed memory space or i/o
device will complete the transfer.
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
bhe_n
bhe_n
Additionally, bhe_n and ad0 encode the
following bus information:
ad0
bhe_n Bus Status
0
0
1
1
0
1
0
1
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
(Enhanced Mode)
Note: bhe_n is used as refresh_n in the
IA188XL.
busy
test_n/busy
47
29
46
busy. Input. Active High. Used in Enhanced
Mode. When the busy input is asserted, it
causes the IA186XL to suspend operation
during the execution of the Intel 80C187
Numerics Coprocessor instructions.
Operation resumes when the pin is sampled
low.
clkout
den_n
clkout
den_n
56
39
19
38
36
56
clock output. Output. The clkout pin
provides a timing reference for inputs and
outputs of the IA186XL. This clock output is
one-half the input clock (clkin) frequency.
The clkout signal has a 50% duty cycle,
transitioning every falling edge of clkin.
data enable. Output. Active Low. This signal
is used to enable bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data are to be
transferred on the bus.
drq0
drq1
drq0
drq1
18
19
61
60
79
78
dma request 0 or 1. Input. Asserted high by
an external device to request DMA Channel 0
or 1 to perform a transfer. These signals are
level-triggered and internally synchronized.
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