IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
4.9
Ready- and Wait-State Programming
Each of the memory or peripheral chip-select lines can have a ready signal programmed that can
be the ardy or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and
MPCS) have a single bit that selects if the external ready signal is to be used or not (R2, Bit [2]).
R1 and R0 (Bits [1–0]) in these registers control the number of wait states that are inserted
during each access to a memory or peripheral location (from 0 to 3). The control registers for
pcs3_n–pcs0_n use three bits, R3, R1–R0 (Bit [3] and Bits [1–0]) to provide 5, 7, 9, and 15 wait
states in addition to the original values of 0–3 wait states.
When an external ready has been selected as required, internally programmed wait states will
always be completed before the external ready can finish or extend a bus cycle. Consider a
system in which the number of wait states to be inserted has been set to three. The external
ready pin is sampled by the processor during the first wait cycle. If the ready is asserted, the
access is completed after seven cycles (4 cycles plus 3 wait cycles). If the ready is not asserted,
during the first wait cycle the access is prolonged until ready is asserted and two more wait states
are inserted followed by t4. The ardy signal is an asynchronous ready with a pin that is active
high and accepts a rising edge asynchronous to clkouta. However, an additional clock period
may be necessary if the falling edge of ardy is not synchronized to clkouta.
4.10 Chip-Select Overlap
Overlapping chip selects are those configurations in which more than one chip select is asserted
for the same physical address. If PCS is configured in I/O space with LCS or any other chip
select configured for memory, address 00000h is not overlapping the chip selects.
It is not recommended that multiple chip-select signals be asserted for the same physical address,
although it may be unavoidable in certain systems. If this is the case, all overlapping chip selects
must have the same external ready configuration and the same number of wait states to be
inserted into access cycles.
Internal signals are employed to access the peripheral control block (PCB). These signals serve
as chip selects that are configured with no wait states and no external ready. Only when these
chip selects are configured in the same manner can the PCB be programmed with addresses that
overlap external chip selects.
Care should be exercised in the use of the DA bit in the LMCS or UMCS registers when
overlapping an additional chip select with either the lcs_n or ucs_n chip selects. Setting the DA
bit to “1” prevents the address from being driven onto the AD bus for all accesses for which the
respective chip select is active, including those for which the multiple selects are active.
The mcs_n and pcs_n pins are dual-purpose pins, either as chip selects or PIO inputs or outputs.
However, their respective ready- and wait-state configurations for their chip-select function will
be in effect regardless of the function for which they are actually programmed. Their ready- and
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