IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
9.
Errata
The following errata are associated with Version 03 of the IA186EM/IA188EM. A workaround
to the identified problem has been provided where possible.
9.1
Errata Summary
Table 97 presents a summary of errata.
Table 97. Summary of Errata
Errata
No.
Problem
Ver. 03
Exists
1
There is a difference in how priority of timer interrupts are asserted between the
original AMD part and the Innovasic part.
2
3
4
5
6
7
Lock up just after reset is released.
Exists
Exists
Exists
Exists
Exists
Exists
Intermittent startup.
Timer Operation in continuous mode.
DMA interrupt will not bring device out of halt state.
Does not clear the interrupt request bit for INT0 upon entering the ISR.
There is a difference in how hardware handshaking for UARTs during a bus hold
cycle is handled between the original AMD part and the Innovasic part.
9.2
Errata Detail
Errata No. 1
Problem: There is a difference in how priority of timer interrupts are asserted between the
original AMD part and the Innovasic part.
Description: In the original AMD part, timer interrupts cannot be interrupted by another timer
interrupt, even if the new timer interrupt is of a higher priority. The Innovasic part will interrupt
a timer interrupt with a higher-priority timer interrupt. Additionally, if a lower-priority timer
interrupt is interrupted with a higher-priority timer interrupt and another incident of the lower-
priority interrupt occurs during the processing of the higher-priority interrupt, upon execution of
the EOI, a new lower-priority interrupt will be initiated, possibly orphaning the original lower-
priority timer interrupt.
Workaround: When using nested interrupts, at the beginning of the interrupt routine before the
global interrupts are enabled with a CLI, timer interrupts must be specifically masked. At the
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