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AM188EM-20VIW 参数 Datasheet PDF下载

AM188EM-20VIW图片预览
型号: AM188EM-20VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 146 页 / 1574 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EM/IA188EM  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
February 25, 2011  
Table 83. Read Cycle Timing  
a
a
No.  
Name  
Description  
Min  
Max  
General Timing Requirements  
1
2
tDVCL  
tCLDX  
Data in Setup  
Data in Hold  
10  
0
General Timing Responses  
3
4
5
6
8
9
tCHSV  
tCLSH  
tCLAV  
tCLAX  
tCHDX  
tCHLH  
Status Active Delay  
0
0
0
0
0
0
6
6
Status Inactive Delay  
ad Address Valid Delay  
Address Hold  
12  
12  
Status Hold Time  
ale Active Delay  
8
10 tLHLL  
11 tCHLL  
12 tAVLL  
13 tLLAX  
14 tAVCH  
15 tCLAZ  
ale Width  
tCLCH-5  
ale Inactive Delay  
0
8
ad Address Valid to ale Low  
ad Address Hold from ale Inactive  
ad Address Valid to Clock High  
ad Address Float Delay  
tCLCH  
tCHCL  
0
0
12  
12  
16 tCLCSV mcs_n/pcs_n Inactive Delay  
0
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive  
18 tCHCSX mcs_n/pcs_n Inactive Delay  
tCLCH  
0
0
12  
19 tDXDL  
den_n Inactive to dt/r_n Low  
20 tCVCTV Control Active Delay 1  
21 tCVDEX den_n Inactive Delay  
22 tCHCTV Control Active Delay 2  
0
10  
9
0
0
10  
23 tLHAV  
ale High to Address Valid  
7.5  
Read Cycle Timing Responses  
24 tAZRL  
25 tCLRL  
26 tRLRH  
27 tCLRH  
28 tRHLH  
29 tRHAV  
66 tAVRL  
ad Address Float to rd_n Active  
0
10  
rd_n Active Delay  
0
rd_n Pulse Width  
tCLCL  
rd_n Inactive Delay  
0
10  
rd_n Inactive to ale High  
rd_n Inactive to ad Address Active  
a Address Valid to rd_n Low  
tCLCH  
tCLCL  
tCLCL + tCHCL  
67 tCHCSV clkouta High to lcs_n/usc_n Valid  
0
0
9
68 tCHAV  
clkouta High to a Address Valid  
8
a
In nanoseconds.  
®
IA211050831-19  
http://www.Innovasic.com  
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