IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
If wlb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle. The
address/data bus is tristated during a bus hold or reset.
2.2.5 ale—Address Latch Enable (synchronous output)
This signal indicates the presence of an address on the address bus (ad15–ad0 for the IA186ES or
ao15–ao8 and ad7–ad0 for the IA188ES), which is guaranteed to be valid on the falling edge of
ale.
In ONCE mode, this pin is tristated but not during bus hold or reset.
2.2.6 ardy—Asynchronous Ready (level-sensitive asynchronous input)
This asynchronous signal provides an indication to the microcontroller that the addressed I/O
device or memory space will complete a data transfer. This active high signal is asynchronous
with respect to clkouta. If the falling edge of ardy is not synchronized to clkouta, an additional
clock cycle may be added. The ardy or srdy must be synchronized to clkouta to guarantee the
number of inserted wait states.
The ardy should be tied high to maintain a permanent assertion of the ready condition. On the
other hand, if the ardy signal is not used by the system, it should be tied low, which passes
control to the srdy signal.
2.2.7 bhe_n/aden_n (IA186ES only)—Bus High Enable (synchronous output with
tristate)/Address Enable (input with internal pullup)
The bhe_n–bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus
(upper, lower, or both) are involved in the current memory access bus cycle, as shown in
Table 9.
Table 9. Bus Cycle Types for bhe_n and ad0
bhe_n ad0 Type of Bus Cycle
0
0
1
1
0
1
0
1
Word Transfer
High Byte Transfer (Bits [15–8])
Low Byte Transfer (Bits [7–0])
Refresh
The bhe_n does not require latching and during bus hold and reset is tristated. It is asserted
during t1 and remains so through t3 and tw.
The high- and low-byte write enable functions of bhe_n and ad0 are performed by whb_n and
wlb_n, respectively.
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