IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
5.1.1 RELREG (0feh)
The Peripheral Control Block RELocation REGister maps the entire Peripheral Control Block
Register Bank to either I/O or memory space. In addition, RELREG contains a bit that places
the interrupt controller in either master or slave mode. The RELREG contains 20ffh at reset (see
Table 17).
Table 17. Peripheral Control Block Relocation Register
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
Reserved S/Mn Reserved IO/Mn
RA [19–8]
Bit [15]—Reserved.
Bit [14]—S/Mn → When set to 1, this bit places the interrupt controller into slave mode.
When 0, it is in master mode.
Bit [13]—Reserved.
Bit [12]—IO/Mn → When set to 1, the Peripheral Control Block is mapped into memory
space. When 0, this bit maps the Peripheral Control Block Register Bank into IO space.
Bits [11–0]—RA [19–8] → Sets the base address (upper 12 bits) of the Peripheral
Control Block Register Bank. RA [7–0] default to zero. When Bit [12] (IO/Mn) is set
to 1, RA [19–16] are ignored.
5.1.2 RESCON (0f6h)
The RESet CONfiguration Register latches user-defined information present at specified pins at
the rising edge of reset. The contents of this register are read-only and remain valid until the
next reset. The RESCON contains user-defined information at reset (see Table 18).
Table 18. Reset Configuration Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RC [15–0]
Bits [15–0]—RC [15–0] → At the rising edge of reset, the values of specified pins
(ad15–ad0 for the IA186ES and ao15–ao8 and ad7–ad0 for the IA188ES) are latched into
this register.
5.1.3 PRL (0f4h)
The Processor Release Level Register contains a code corresponding to the latest processor
production release. The PRL is a read-only register. The PRL contains 1100h (see Table 19).
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