IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
2.2.35 rfsh2_n/aden_n (IA188ES only)—Refresh 2 (synchronous output with
tristate)/Address Enable (input with internal pullup)
The rfsh2_n indicates that a DRAM refresh cycle is being performed when it is asserted low.
However, this is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead.
If aden_n is held high during POR, the ad bus (ao15–ao8 and ad7–ad0) is controlled during the
address portion of the LCS and UCS bus cycles by the DA bit (Bit [7]) in the LMCS and UMCS
registers. If the DA bit is 1, the address is accessed on the a19–a0 pins reducing power
consumption. The weak pullup on this pin obviates the necessity of an external pullup.
If this pin is held low during POR, the ad bus is used for both addresses and data without regard
for the setting of the DA bits. The rfsh2_n/aden_n is sampled one crystal clock cycle after the
rising edge of res_n and is tristated during bus holds and ONCE mode.
2.2.36 rts0_n/rtr0_n/pio20—Ready-to-Send 0 (asynchronous output)/Ready-to-Receive 0
(asynchronous input)
The rts0-n is the Ready-to-Send signal for asynchronous serial port 0 when the RTS0 bit (Bit [3])
in the auxiliary control register (AUXCON) is 1 and hardware flow control is enabled for this
port (FC bit [Bit (9)] in the serial port 1 control register [SP1CT]). This signal is asserted when
the serial port transmit register contains untransmitted data.
The rtr0-n is the Ready-to-Receive signal for asynchronous serial port 0 when the rts0 bit
(Bit [3]) in the auxiliary control register (AUXCON) is 0 and hardware flow control is enabled
for this port (FC bit [Bit (9)] in the serial port 1 control register [SP1CT]). This signal is asserted
when the serial port receive register does not contain valid unread data.
2.2.37 rxd0_n/pio23—Receive Data 0 (asynchronous input)
This signal connects asynchronous serial receive data from the system to the asynchronous Serial
Port 0.
2.2.38 rxd1_n/pio28—Receive Data 1 (asynchronous input)
This signal connects asynchronous serial receive data from the system to the asynchronous Serial
Port 1.
2.2.39 s2_n–s0_n—Bus Cycle Status (synchronous outputs with tristate)
These three signals inform the system of the type of bus cycle is in progress. The s2_n may be
used to indicate whether the current access is to memory or I/O, and s1_n may be used to
indicate whether data is being transmitted or received. These signals are tristated during bus
hold and hold acknowledge. The coding for these pins is presented in Table 10.
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