IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Bit [4]—TMR1 Timer 1 Interrupt Mask → This bit provides an indication of the state of
the mask bit in the Timer Interrupt Control register. When set to 1, it indicates that the
interrupt request is masked.
Bits [3–2]—D1–D0 DMA Channel Interrupt Mask → This bit provides an indication of
the state of the mask bit in the respective DMA channel Interrupt Control register. When
set to 1, it indicates that the interrupt request is masked.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt Mask → This bit provides an indication of the state of
the mask bit in the Timer Interrupt Control register. When set to 1, it indicates that the
interrupt request is masked.
5.1.49 POLLST (026h) (Master Mode)
POLL STatus Register. This register reflects the current state of the Poll register and can be read
without affecting its contents. However, when the Poll Register is read, it causes the current
interrupt to be acknowledged and replaced by the next interrupt. The poll status register is read-
only (see Table 71).
Table 71. POLL Status Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IREQ
Reserved
S4–S0
Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending.
During this state the S4–S0 bits contain valid data.
Bits [14–5]—Reserved.
Bits [4–0]—S4–S0 Poll Status → These bits show the interrupt type of the highest
priority pending interrupt.
The interrupt service routine does not begin execution automatically with the IS bit set. Rather,
the application software must execute the appropriate ISR.
5.1.50 POLL (024h) (Master Mode)
POLL Register. When the Poll Register is read, it causes the current interrupt to be
acknowledged and be replaced by the next interrupt. The poll status register reflects the current
state of the Poll register and can be read without affecting its contents. The POLL register is
read-only (see Table 72).
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