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AM186EM-25VIW 参数 Datasheet PDF下载

AM186EM-25VIW图片预览
型号: AM186EM-25VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 146 页 / 1574 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EM/IA188EM  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
February 25, 2011  
5.1.37 T2INTCON (03ah), T1INTCON (038h), and T0INTCON (032h) (Slave Mode)  
Timer INTerrupt CONtrol Register. The three timers, Timer 2, Timer 1, and Timer 0, each have  
an interrupt control register, whereas in master mode all three are masked and prioritized in one  
register (TCUCON). The value of these registers is 000Fh at reset (see Table 59).  
Table 59. Timer Interrupt Control Register  
15 14 13 12 11 10  
Reserved  
9
8
7
6
5
4
3
2
1
0
MSK PR2PR0  
Bits [154]Reserved Set to 0.  
Bit [3]MSK Mask Any of the interrupt sources may cause an interrupt if the MSK  
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.  
Bits [20]PR2PR0 Priority These bits define the priority of the serial port  
interrupts in relation to other interrupt signals. The interrupt priority is the lowest at 7 at  
reset. The values of PR2PR0 are shown above.  
5.1.38 DMA1CON/INT6CON (036h) and DMA0CON/INT5CON (034h) (Master Mode)  
DMA and INTerrupt CONtrol Register. The DMA0 and DMA1 interrupts have interrupt type  
0ah and 0bh, respectively. These pins are configured as external interrupts or DMA requests in  
the respective DMA Control register. The value of these registers is 000Fh at reset (see  
Table 60).  
Table 60. DMA and Interrupt Control Register (Master Mode)  
15 14 13 12 11 10  
Reserved  
9
8
7
6
5
4
3
2
1
0
MSK PR2PR0  
Bits [154]Reserved Set to 0.  
Bit [3]MSK Mask Any of the interrupt sources may cause an interrupt if the MSK  
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.  
Bits [20]PR2PR0 Priority These bits define the priority of the serial port  
interrupts in relation to other interrupt signals. The interrupt priority is the lowest at 7 at  
reset. The values of PR2PR0 are shown above.  
5.1.39 DMA1CON/INT6 (036h) and DMA0CON/INT5 (034h) (Slave Mode)  
DMA and INTerrupt CONtrol Register. The two DMA control registers maintain their original  
functions and addressing that they possessed in Master Mode. These pins are configured as  
®
IA211050831-19  
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