Forced Quasi Resonant ZVS flyback controller
Representative Block Diagram
2
Representative Block Diagram
Figure 3 shows a simplified top level block diagram of the IC functionality.
HV
XDPS21081
HV Startup-cell
Bang-Bang Ctrl
VVCCBBoff = 20.5 V
Closed/Open
Startup-Cell
Driver
VVCCBBonAR/LM = 9 V
Vbulk Brown-out
Protection
IHVBO = 0.443 mA
QM
D1
Vbulk
Vbulk Brown-in
measurement
Protection
Overtemperature
Detection
TJOTP = 130 °C
IHVBI = 1.15 mA
RM
&
VCC Brown-in
VCC
Protection
VVCCBI = 9.1 V
Protection
Modes
HW Reset
UVLO
VVCCon = 20.5 V
Auto Restart
Mode
Power
Management
VVCCoffx = 7.2 V / 9.6 V
Vout OV
Protection
Latch
Mode
Vout reflected Voltage
Measurement
ZCD
1 kꢀ
VZCDOVP = 2.75 V
Soft-Start
ZVS ontime
Open Loop Timer
tMFIOH = 31.3 ms
Zero Crossing Detection
Gate Driver
FFR Mode
With ZVS Pulse
Generation
PWM
Logic
Frequency Law
fSW
GD0
C2
VCSPK
VMFIO
VMFIOH = 2.41 V
PDC
VVDDP = 3.3 V
VMFIO
Gate Driver
RMFIOPU
GD1
Burst Mode Function
Vcs_offset
MFIO
C3
VMFIOBMEX1
BM Exit
C5
VMFIOBMWK
on-phase
off-phase
BM 2-point
Regulation
BM Ctrl
C6
VMFIOBMPA
C7
BM Entry
VMFIOBMEN
Cycle by Cycle Peak Current Ctrl
OCP1
CS
tCSLEB
VCSPK
10kꢀ
1 kꢀ
1 pF
Auto Restart
Input Detection
2nd Level Overcurrent Detection
OCP2
tCSOCP2BL
VCSOCP2 = 0.6 V
VVDDP = 3.3 V
IGPIOLPU
UART
Communication
Parameter
Configuration
GPIO
Figure 3
Representative Block Diagram of XDPS21081
Data Sheet
5
Revision 2.0
2020-08-20
INFINEON [ Infineon ]
