Forced Quasi Resonant ZVS flyback controller
Pin Configuration and Functionality
1
Pin Configuration and Functionality
The pin configuration is shown in Figure 2 and the functions are described in Table 1.
1
2
3
4
12
11
10
9
ZCD
MFIO
GPIO
CS
GND
VCC
GD0
GD1
5
6
8
7
HV
HV
HV
HV
PG-DSO-12-20
Figure 2
Pin Configuration of XDPS21081
Table 1
Symbol
ZCD
Pin Definitions and Functions
Pin
Type
Function
1
I
Zero Crossing Detection
ZCD pin is connected to an auxiliary winding for zero crossing detection and positive
pin voltage measurement.
2
I
Multi-Functional Input Output
MFIO pin is connected to an optocoupler that provides an amplified error signal for
the PWM mode operation.
MFIO
GPIO
CS
3
IO
I
Digital General Purpose Input Output
GPIO pin provides an UART interface until brown-in. It is switched to weak
pull down mode and disabled UART function during normal operation.
Current Sense
4
CS pin is connected via a resistor in series to an external shunt resistor and
the source of the power MOSFET.
HV
5, 6, 7, 8
I
High Voltage Input
HV pin is connected to the rectified bulk voltage. An internally connected 600
V HV startup-cell is used for initial VCC charge. Furthermore brown-in and
brownout detection is provided.
GD1
9
I
FQR ZVS Signal Gate Driver Output
GD1 pin provides a gate driver pulse signal to initiate the forced quasi
resonant ZVS mode operation.
GD0
VCC
GND
10
11
12
O
I
Gate Driver Output
Output for directly driving the main power MOSFET.
Positive Voltage Supply
IC power supply.
O
Power and Signal Ground
Data Sheet
4
Revision 2.0
2020-08-20
INFINEON [ Infineon ]
