TLE 6365
Circuit Description
Below some important sections of the TLE 6365 are described in more detail.
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed.
In case of VCC power down (VCC < VRT for t > tRR) a logic LOW signal is generated at the
pin RO to reset an external microcontroller. When the level of VCC reaches the reset
threshold VRT, the signal at RO remains LOW for the Power-up reset delay time tRD
before switching to HIGH. If VCC drops below the reset threshold VRT for a time extending
the reset reaction time tRR, the reset circuit is activated and a power down sequence of
period tRD is initiated. The reset reaction time tRR avoids wrong triggering caused by short
“glitches” on the VCC-line.
< tRR
< tRD
VCC
Typ. 4.70 V
Typ. 4.65 V
VPG
VRT
1 V
Start Up
ON Delay
ON Delay
Stopped
t
t
ON Delay
Started
RO
H
Invalid
Invalid
Invalid
L
tRR
tRD
tRD
Power
Start-Up
Normal
Failed
N
Failed
Normal
AET03325.VSD
Figure 3
Reset Function
Data Sheet
9
Rev. 1.9, 2007-07-30
INFINEON [ Infineon ]
