TLE 6244X
When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by
the µsec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access.
The received µsec-bus bit stream (D0... D15) is latched into a 16-bit register by the rising edge at
SSY. Power stages 1...7 and 9...16 are switched according to bits D0...D7 and D9...D15:
µsec-bus control of
power stage
µsec-bus
D8
control of
power stage
D0
OUT14
µsec-bus Test
Bit
D1
D2
D3
D4
D5
D6
D7
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
D9
OUT11
OUT10
OUT9
D10
D11
D12
D13
D14
D15
OUT12
OUT13
OUT16
OUT15
Bit Dx = 0:
Power stage OUTx is switched on
Power stage OUTx is switched off
FFFFH
Bit Dx = 1:
State of reset:
Because the power stage 8 is not controlled by the µsec-bus-interface, the corresponding bit D8
can be used as test bit, that can be read back by the SPI-interface (see register RD_INP1).
If the µsec-bus-interface is used to control the power stages, the input pins IN1..IN5 and
IN8...IN15 can be used as input port expander by reading the status of the input pins by the SPI-
commands RD_INP1/2.
Final Data Sheet
31
V4.2, 2003-08-29
INFINEON [ Infineon ]
