TDA5235
Functional Description
2.4
Functional Block Description
Architecture Overview
2.4.1
A fully integrated Sigma-Delta Fractional-N PLL Synthesizer covers the frequency bands
300-320 MHz, 425-450 MHz, 863-870 MHz, 902-928 MHz with a high frequency
resolution, using only one VCO running at around 3.6 GHz.
For Multi-Configuration applications requiring different RF channels a very good channel
separation is essential. To achieve the necessary high sensitivity and selectivity a double
down conversion super-heterodyne architecture is used. The first IF frequency is located
around 10.7 MHz and the second IF frequency around 274 kHz. For both IF frequencies
an adjustment-free image frequency rejection feature is realized. In the second IF
domain the filtering is done with an on-chip third order bandpass polyphase filter. A multi-
stage bandpass limiter completes the RF/IF path of the receiver. For Single-Channel
applications with relaxed requirements to selectivity, a single down conversion low-IF
scheme can be selected.
For Multi-Configuration systems requiring different RF channels where even higher
channel separation is required, up to two (switchable) external ceramic (CER) filters can
be used to improve the selectivity.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via an anti-aliasing filter this signal feeds an ADC
with 10 bits resolution.
The harmonic suppressed limiter output signal feeds a digital FSK demodulator. This
block demodulates the FSK data and delivers an AFC signal which controls the divider
factor of the PLL synthesizer.
A digital receiver, which comprises RSSI peak detectors, a matched data filter, a clock
and data recovery, a data slicer, a frame synchronization and a data FIFO, decodes the
received ASK or FSK data stream. The recovered data and clock signals are accessible
via 2 separate pins. The FIFO data buffer is accessible via the SPI bus interface.
The crystal oscillator serves as the reference frequency for the PLL phase detector, the
clock signal of the Sigma-Delta modulator and divided by two as the 2nd local oscillator
signal. To accelerate the start up time of the crystal oscillator two modes are selectable:
a Low Power Mode (with lower precision) and a High Precision Mode.
Data Sheet
17
V1.0, 2010-02-19
INFINEON [ Infineon ]
