TDA5235
Functional Description
2.6.2
Polling Timer Unit
SPM
Reference-Timer
(8 Bit)
SPM
On-Off-Timer
(14 Bit)
SPM
fsys / 64
fRT
fOnOff
Active-Idle Period Timer
(5 / 8 Bit)
Self-Polling-Mode (SPM)
FSM
No WU
Polling Mode
to
Master-Control-Unit
Figure 79
Polling Timer Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (fsys/64) into the slower
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5235 is able to handle up to two different sets of configurations automatically.
Data Sheet
112
V1.0, 2010-02-19
INFINEON [ Infineon ]
