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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
HistoryChanges from Version 0.7 to Version 1.0  
Added footnote 5) for IEXTFLEX  
Changes in table 'Module Current Consumption'  
Changed value and condition of parameter IEXTLVDS  
Added footnote 3) to IEXTLVDS  
Added footnote 5) to IDDM  
Changed footnote 8) for ISCRIDLE  
Changes in table 'Module Core Current Consumption'  
Changed footnote 1) for IDDHSM  
Changed footnote for IDDSPU2  
Removed parameter IDDSPU1  
Removed parameter IDDSPULJ1  
Changes in chapter “Supply Ramp-up and Ramp-down Behavior”  
Changed Figure and textual description for “Single supply mode (a)”  
Changed Figure and textual description for “Single supply mode (e)”  
Changed Figure and textual description for “Single supply mode (d)”  
Changed Figure and textual description for “Single supply mode (h)”  
Changes in table 'Reset'  
Added parameter tWARMRSTSEQ  
Shift typ limit to max limits for mode0 and mode1 and removed typ limits for parameter tSCR  
Changes in table 'EVR33 LDO'  
Added footnote 7) for dVOUT / dIOUT  
Changes in table 'Supply Monitors'  
Changed condition of parameter VRST33  
Changed condition of parameter VRSTC  
Changed values of parameter VEXTMON  
Changed footnote 2) for VEXTPRIUV, VDDP3PRIUV, VDDPRIUV,  
Changed footnote 3) for VDDP3PRIUV, VDDPRIUV,  
Added footnote 5) for VEXTMON, VDDP3MON, VDDMON  
Changes in table 'EVRC SMPS External Components'  
Add values of parameter 'LDC' for condition 0.8MHz  
Changed chapter naming from 'Phase Locked Loop (PLL)' to 'System Phase Locked Loop (SYS_PLL)'  
Changes in table 'PLL System'  
Removed parameter values of 'fMV'  
Changes in table 'QSPI Master Mode Timing'  
Added footnote 1) for all parameters  
Changes in table 'MSC LVDS clock/data'  
Added footnote 3) for all parameters  
Changes in chapter 'HSCT Parameters'  
Added table for “HSCT”  
Add chapter FSP Parameter  
Changes in table 'Flash'  
Changed description of parameter of NDFD  
Data Sheet  
540  
V 1.2, 2021-03  
OPEN MARKET VERSION  
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