TC39x BC/BD-Step
HistoryChanges from Version 0.4 to Version 0.6
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Change description of SR_V_DD from 'External VDD supply ramp' to 'External VDD supply ramp-up and
ramp-down slope'
Change description of SR_V_DDM from 'External VDDM supply ramp' to 'External VDDM supply ramp-up and
ramp-down slope'
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Changes in table 'EVRC SMPS' of PMS/EVRC SMPS
Change name of EVRC SMPS from EVR13 SMPS to EVRC SMPS
Changes in table 'EVRC SMPS External components' of PMS/EVRC SMPS
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Change name of EVRC SMPS External components from EVR13 SMPS External components to EVRC
SMPS External components
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Changes in section JTAG Parameters
Update figure Test Clock Timing (TCK)
Changes in section DAP Parameters
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Combine figures Test Clock Timing (DAP0), DAP Timing Host to Device, and DAP Timing Device to Host
(DAP1 and DAP2 pins) into single figure DAP Timing
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Add t14 for condition F=40MHz
Add t15 for condition F=40MHz
Add t16 for condition F=40MHz
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Changes in table 'Master Mode strong sharp (ss) output pads' of ASCLIN
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Change min value of t51 from -3 ns to -3.5 ns
Change note of t51 from '3 ns' to '3.5 ns'
Change max value of t510 from 3 ns to 3.5 ns
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Changes in table 'Master Mode Timing, LVDS output pads for data and clock' of QSPI
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Change max value of t51 from 3 ns to 4 ns
Change min value of t52 from 17 ns to 18 ns
Changes in table 'Strong sharp (ss) driver for clock/data valid for 5V' of MSC
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Change note of t45 from '-3 ns' to '-4 ns'
Change min value of t44 from -3 ns to -4 ns
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Changes in table 'ETH RGMII Signal Timing Parameters valid for 3.3V' of Ethernet
Add parameter t21
Changes in table 'ETH RMII Signal Timing Parameters valid for 3.3V' of Ethernet
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Change description of t16 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; setup
time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time'
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Change description of t17 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; hold
time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time'
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Changes in table 'HSCT - Rx/Tx setup timing' of LVDS Pads
Change max value of ttx from 250 ns to 280 ns
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Removed section CIF
SDMMC
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Change note of t5 from 'CL ≤ 30pF' to 'CL ≤ 30pF, VEXT = 3.3V'
Change min value of t5 from -3 ns to 3 ns
Change description of t5 from 'Data output delay time' to 'Data output valid time before rising clock edge'
Change note of t6 from ''CL ≤ 30pF'' to ''CL ≤ 30pF, VEXT = 3.3V''
Change note of t6 from 'max' to 'min'
Data Sheet
528
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
