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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
HistoryChanges from Version 0.4 to Version 0.6  
Change note of ISCRSB from 'SCR power pattern; fSYS_SCR = 20MHz; TJ=150°C' to 'SCR power pattern incl.  
PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C'  
Change note of ISCRSB from 'real power pattern; fSYS_SCR = 70kHz; TJ=25°C' to 'SCR power pattern incl.  
PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C'  
Change typ value of ISCRSB from 0.025 mA to 0.190 mA  
Change description of ISCRSB from 'SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB  
supply pin' to 'SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply  
pin'  
Change note of IDDM from ''real power pattern ; current for EDSADC module only; 11 EDSADC channels  
active.'' to ''real power pattern; current for EDSADC modules only and EVADC modules are inactive; 11  
EDSADC channels active continuously.''  
Change note of IDDM from '66 mA' to '44 mA'  
Change note of IDDM from 'max power pattern; All EDSADC channels active 100% time.' to 'max power  
pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active  
continuously.'  
Change max value of IDDM from 84 mA to 63 mA  
Change note of IDDM from 'real pattern;12 EVADC modules active' to 'real power pattern; current for EVADC  
modules only and EDSADC modules are inactive; 12 EVADC modules active.'  
Change note of IDDM from 'max power pattern; All EVADC modules are active 100% time' to 'max power  
pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active.'  
Change max value of IDDM from 26 mA to 20 mA  
Change max value of IDDM from 82 mA to 60 mA  
Change max value of IDDTOT from 1506 mA to 1536 mA  
Change note of IDDTOTDC3 from 'real power pattern; VEXT = 3.3V; TJ=160°C' to 'real power pattern; EVRC  
reset settings with 72% efficiency; VEXT = 3.3V; TJ=160°C'  
Change max value of IDDTOTDC3 from 830 mA to 980 mA  
Change description of IDDTOTDC3 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum  
of all currents with DC-DC EVRC regulator active'  
Change note of IDDTOTDC5 from 'real power pattern; VEXT = 5V; TJ=160°C' to 'real power pattern; EVRC reset  
settings with 72% efficiency; VEXT = 5V; TJ=160°C'  
Change max value of IDDTOTDC5 from 600 mA to 670 mA  
Change description of IDDTOTDC5 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum  
of all currents with DC-DC EVRC regulator active'  
Change note of ISLEEP from '10 mA' to '25 mA'  
Change note of PD from 't.b.d. mW' to '3220 mW'  
Change max value of PD from 2560 mW to 2500 mW  
Change max value of IEVRSB from 4 mA to 8 mA  
Change note of IEVRSB from 'real power pattern; PMS/EVR module current considered without SCR and  
Standby RAM' to 'real power pattern; PMS/EVR module current considered without SCR and Standby RAM  
during RUN mode.'  
Change max value of IDDTOT from 1690 mA to 1720 mA  
Reset  
Change min value of tPOH from 100 ns to 150 ns  
Change note of tBP from 'dV/dT=1V/ms. including EVR ramp-up and Firmware execution time; RAM  
initialization and HSM boot time is not included' to 'dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time after  
Data Sheet  
526  
V 1.2, 2021-03  
OPEN MARKET VERSION  
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