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SAK-TC1767-256F80HL 参数 Datasheet PDF下载

SAK-TC1767-256F80HL图片预览
型号: SAK-TC1767-256F80HL
PDF下载: 下载PDF文件 查看货源
内容描述: 32位单芯片微控制器 [32-Bit Single-Chip Microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 126 页 / 832 K
品牌: INFINEON [ Infineon ]
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TC1767  
Introduction  
• For further operating conditions see data sheet section “Flash Memory Parameters”.  
Data Flash Features and Functions  
• 64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size.  
• 64 bit read interface.  
• Erase/program one bank while data read access from the other bank.  
• Programming one bank while erasing the other bank using an automatic  
suspend/resume function.  
• Dynamic correction of single-bit errors during read access.  
• Sector architecture:  
– Two sectors of equal size.  
– Each sector separately erasable.  
• 128 byte pages to be written in one step.  
• Operational control per command sequences (unlock sequences, same as those of  
Program Flash) for protection against unintended operation.  
• End-of-busy as well as error reporting with interrupt and bus error trap.  
• Write state machine for automatic program and erase.  
• Margin check for detection of problematic Flash bits.  
• Endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per  
sector are allowed, with a retention of min. 5 years.  
• Dedicated DFlash status information.  
• Other characteristics: Same as Program Flash.  
2.3.7  
Data Access Overlay  
The data overlay functionality provides the capability to redirect data accesses by the  
TriCore to program memory (segments 8H and AH) called “target memory” to a different  
memory called “overlay memory”.  
Depending on the device the following overlay memories can be available:  
• Overlay SRAM in the PMU.  
• Emulation Memory1).  
• External memory2).  
This functionality makes it possible, for example, to modify the application’s test and  
calibration parameters (which are typically stored in the program memory) during run  
time of a program.  
As the address translation is implemented in the DMI, it affects only data accesses  
(reads and writes) of the TriCore. Instruction fetches by the TriCore or accesses by any  
other master (including the debug interface) are not redirected.  
1) Only available in Emulation Device “ED”.  
2) Only available in Emulation Device with EBU.  
Data Sheet  
27  
V1.3, 2009-09  
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