TC1762
Preliminary
General Device Information
2.3
Pin Configuration
Figure 2-3 shows the TC1762 pin configuration.
OCDSDBG0/OUT40/IN40/P5.0
OCDSDBG1/OUT41/IN41/P5.1
OCDSDBG2/OUT42/IN42/P5.2
OCDSDBG3/OUT43/IN43/P5.3
OCDSDBG4/OUT44/IN44/P5.4
OCDSDBG5/OUT45/IN45/P5.5
OCDSDBG6/OUT46/IN46/P5.6
OCDSDBG7/OUT47/IN47/P5.7
1
2
3
4
5
6
7
8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
P3.4/MTSR0
P3.7/SLSI0/SLSO02
P3.3/MRST0
P3.2/SCLK0
P3.8/SLSO06/TXD1A
P3.6/SLSO01/SLSO01
P3.5/SLSO00/SLSO00
VSS
VDDP
TRCLK
VDD
VDDP
VSS
9
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
HDRST
PORST
NMI
BYPASS
TESTMODE
BRKIN
BRKOUT
TCK
TRST
TDO
TMS
TDI
P1.7/IN23/OUT23/OUT79
P1.6/IN22/OUT22/OUT78
P1.5/IN21/OUT21/OUT77
P1.4/IN20/EMG_IN/OUT20/OUT76
VDDOSC3
VDDOSC
VSSOSC
XTAL2
XTAL1
VSS
OCDSDBG8/RDATA0B/P5.8
OCDSDBG9/RVALID0B/P5.9
OCDSDBG10/RREADY0B/P5.10
OCDSDBG11/RCLK0B/P5.11
OCDSDBG12/TDATA0/P5.12
OCDSDBG13/TVALID0B/P5.13
OCDSDBG14/TREADY0B/P5.14
OCDSDBG15/TCLK0/P5.15
N.C.
VSSAF
VDDAF
VDDMF
VSSMF
VFAREF
VFAGND
TC1762
AN35
AN34
AN33
AN32
AN31
AN30
AN29
AN28
AN7
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
VDDP
VDD
98
97
96
95
94
93
92
91
P1.3/IN19/OUT19/OUT75
P1.11/IN27/IN51/OUT27/OUT51
P1.10/IN26/IN50/OUT26/OUT50
P1.9/IN25/IN49/OUT25/OUT49
P1.8/IN24/IN48/OUT24/OUT48
P1.2/IN18/OUT18/OUT74
P1.1/IN17/OUT17/OUT73
P1.0/IN16/OUT16/OUT72
P4.3/IN31/IN55/OUT31/OUT55/SYSCLK
N.C.
90
89
MCP06067
Figure 2-3
TC1762 Pinning for PG-LQFP-176-2 Package
Data Sheet
8
V1.0, 2008-04
INFINEON [ Infineon ]
