SAB 82525
SAB 82526
SAF 82525
SAF 82526
Since the on-chip timer of the HSCX must be operated in the external mode (a secondary may
not poll the primary for acknowledgements), time supervisory must be done by the primary
station.
Upon the arrival of an acknowledgement the XFIFO is enabled and an interrupt is forwarded
to the CPU, either the
– message has been acknowledged as positive (XPR interrupt), or the
– message must be repeated (XMR interrupt).
Additionally, the timer can be used under CPU control to provide timer recovery of the
secondary if no acknowledgements are received at all.
Note: The transmission of transparent frames is possible only if the permission to send is
achieved by an S-frame (p = 1) or I-frame.
Semiconductor Group
35
INFINEON [ Infineon ]
