SAB 82525
SAB 82526
SAF 82525
SAF 82526
2.6 Receive Data Flow (Summary)
The following figure gives an overview of the management of the received HDLC frames as
affected by different operating modes.
Ι
FLAG
ADDR
CTRL
CRC
FLAG
MDS1 MDS0 ADM MODE
ADDRESS
CONTROL
DATA
STATUS
RAH1, 2
RAL1, 2
RFIFO
0
0
1
Auto/16
RHCR
RHCR
RHCR
RHCR
RHCR
RSTA
RSTA
RSTA
RSTA
RSTA
RSTA
RAL1, 2
RAH1, 2
RAL1, 2
RAH1, 2
X
RFIFO
RFIFO
RFIFO
RFIFO
RFIFO
0
0
0
1
1
0
1
1
0
0
0
1
0
1
0
Auto/8
RAL1, 2
Non
Auto/16
X
Non
Auto/8
Transparent
Transparent
1
0
RAL1
RAL1
RHCR
ITD00228
Description of Symbols:
Compared with (register)
Note:In case of on 8 Bit Address,
the Control Field starts here!
Processed autonomously
Stored (FIFO, register)
Figure 8
Receive Data Flow of HSCX
Semiconductor Group
26
INFINEON [ Infineon ]
